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Espressif Systems /ESP32-P4 /H264_DMA /COUNTER_RST

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Interpret as COUNTER_RST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_CH0_EXTER_COUNTER_RST)RX_CH0_EXTER_COUNTER_RST 0 (RX_CH1_EXTER_COUNTER_RST)RX_CH1_EXTER_COUNTER_RST 0 (RX_CH2_INTER_COUNTER_RST)RX_CH2_INTER_COUNTER_RST 0 (RX_CH5_INTER_COUNTER_RST)RX_CH5_INTER_COUNTER_RST

Description

counter reset register

Fields

RX_CH0_EXTER_COUNTER_RST

Write 1 then write 0 to this bit to reset rx ch0 counter.
RX_CH1_EXTER_COUNTER_RST

Write 1 then write 0 to this bit to reset rx ch1 counter.
RX_CH2_INTER_COUNTER_RST

Write 1 then write 0 to this bit to reset rx ch2 counter.
RX_CH5_INTER_COUNTER_RST

Write 1 then write 0 to this bit to reset rx ch5 counter.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data